Computer Science Laboratory and Exercise 3 (Hardware)

• Web Page: Contains resources and FAQs. Also known as this page.
• Slack: Chat-based support for questions and technical guidance
• There will be staff members on Slack during the hours projects are conducted. Feel free to ask questions on the channel #実験3hw for Computer Science Course Workspace. Students may be able to help each other as well.
• We will try to respond to your questions outside of laboratory hours as well. You are welcome to help each other by answering each other's questions before the faculty member or TA do.
• #実験3hw_random has also been created. You can use it to exchange progress and information, or just to chat.
• If you don't know how to subscribe to the course workspace and #実験3hw on Slack, send an email to the staff.
• Avoid asking questions to faculty members or TAs via DM. Share your problems and solutions with others as they may be helpful to them. If you are too shy, you can send a group DM or email to our staff. We will not respond to DMs other than group DMs.
• We are operating under the free plan for the time being. There are limitations on the access to the most recent messages and we can make only one-to-one voice calls (no screen sharing). Follow the usage and capacity and use it wisely.

• It is used to submit reports to assignments.
• Of course, you can also use it effectively to manage daily changes in your design data.

Overview of the Project

In this project, we will build a microcomputer using a programmable LSI called FPGA.

PowerMedusa board is used to build the microcomputer, and the logic CAD tool Quartus Prime 20.1 is used for logic design. By programming the FPGA on the PowerMedusa board as a processor, the entire board can be made to operate as a single microcomputer.

The architecture of the processor to be implemented follows the SIMPLE architecture. In this project, everything from system design to logic design of this processor is carried out.
The goal of the project is not only to design according to the given specifications and principles, but also to make your own improvements and enhancements. We will also quantitatively evaluate and discuss the effectiveness of various extensions and optimization techniques for processor architectures.

There are three reports to be submitted: an introductory assignment on the design of 7SEG LED circuits and counters, a mid-term report and a final report on the processor design exercise. In the final report, a demonstration and sales talk will also be assigned.

Experiments will be carried out in small groups. Git is used for sharing and version control of the design data in the group. GitHub Classroom will be used to submit the design data for the reports. GitHub Classroom will also be used for debugging consultation.

Finally, in the final demonstration, the students will actually run an application program on the microcomputer you have built in this project.
We will hold a sorting speed contest where you can compete for the performance of the processor you have built. Participation is optional, but encouraged.

What's New

• 2023/4/4
  • The content is updated to AY2024.
• 2022/4/15
  • The top page is translated.

What's New History

Notes on Attending the Project

Read the following pages and reference materials carefully before attending this project.

• Project 3 General Guidance Slide
• Notes on Attending Project 3 Hardware
• Attitude for Using Computer Systems

Calendar

The deadlines for submission of the reports and progress to be made are shown as a guideline.
By the time you submit your mid-term report, it is desirable that a design that can run some instructions is completed and a processor that meets the basic specifications and principles of SIMPLE is essentially ready.

Staff

• E-mail（to be sent to all staff）：le3hw@kuis.kyoto-u.ac.jp
• Debugging Consultation：
  • In-person/Slack during hours, Slack after hours. If you are shy, you may send an email instead.
  • Progress can be made easily if you share the design data you are having problems with on GitHub by creating a branch. Add an explanation to convey what you are having problems with. (Issue management may also be possible. Let's move forward in a way that is mutually easier.)

Assignments/Demonstrations

There are three report assignments/demonstrations: introductory assignment, mid-term report, and final report.
The introductory assignment consists of submission of a report only, while the mid-term and final reports consist of submission of a report and a demonstration.
Each deadline is given as a guideline. Even if the deadline is not met, we will provide sufficient support, so you can proceed according to your own exercise environment and pace. (However, it is not advisable to put off writing the report because it is tedious, and to proceed with the implementation first.)

Git/GitHub

Using Git

Introductory Assignment

Details and Report:

Students are required to design a 7SEG LED drive circuit and a counter individually and submit a report on the details of the design.
Note that this is not an exam answer sheet, but an experimental report.

Submission Deadline:

April 19 (Fri) 13:15

Submission Method:

Submit the report by placing the report and design data as shown in the submission details below and creating a release for the tag name (Tag version) called submit in the repository 2024-intro-[account name] in GitHub Classroom.

The assignment is considered submitted when the release is created.
To resubmit, you must create a new release with a suffix number such as submit-1.

Submission Details:

1. Place the report document (in PDF format only) in the top directory of the remote repository with the file name intro.pdf.
   The document should have a cover page. The cover page should indicate the name of the document, the student number and name, and the date of submission, etc.
2. The design data should be included in this repository.

Processor Design Exercise

• After completing the introductory assignment, start on the processor design exercise.
• Each group will develop his or her own processor based on the SIMPLE architecture.
• The processor is partitioned into functional components, and the design work is shared among the group members.
• Each group will work on their own design and report in the remote repository of 2024-simple-team[team number] in GitHub Classroom. The release of this repository is regarded as the submission of your report and design data.
• By the time of the mid-term report, the specifications of the final processor design should be finalized and documented.
• In the mid-term demonstration, the students will demonstrate partial operation of the processor on an FPGA board.
• For the final demonstration and final report, students will run their application programs on the processor they have built and create documents necessary to operate the processor.

Mid-Term Report

Demonstration [Running demonstration of the processor]

Date and Time: May 10th (Fri) 13:15-16:30

After downloading the designed processor onto the PowerMedusa board, demonstrate that some instructions are running. Be creative in how you show this.

Report [Final specifications of the processor to be designed]

Submission Deadline: May 10th (Fri) 18:15

Submission Method: Submit the report by creating a release for the tag name (Tag version) called middle in the repository of 2024-simple-team[team number] in GitHub Classroom. The assignment is considered submitted when the release is created. To resubmit, you must create a new release with a suffix number such as middle-1.

Materials to be Submitted: Reports as indicated below and design data at the time of the mid-term report.

Content of the Report: Summarize the following information about the final design of the processor. Each document should have a cover page. The cover page should indicate the name of the document, the student number and name, and the date of submission, etc. Create a directory named report_middle at the top of the remote repository, and place each report document (PDF format only) in the directory with the file names shown in blue below.

1. [1 copy per group] Architecture Study Report (File name: architecture_study_report.pdf) "What to achieve"
   1. Specification requirements, design goals, design principles, and features
      • Functionalities to achieve, target values for performance, etc
   2. Acceleration/parallel processing methods
      • Extended instructions, operating frequency, pipelining, parallelization, etc
   3. Performance/cost prediction
      • How many times the performance and amount of hardware compared to SIMPLE/B, and is this a reasonable estimate?
      • Computation time for sorting speed contest, estimating number of cycles, etc.
   4. Considerations, etc.
2. [1 copy per group] System Design Specifications (File name: system_design_spec.pdf) "How to implement"
   • Overview
   • Instruction set architecture
   • Structure and operation
3. [1 copy per person] Functional Design Specifications (File name: function_design_spec-[student number].pdf) "Specific methods of implementation"
   • How was the whole system segmented into components? (Reprint and explain the block diagram in the system design specifications.)
   • External specifications of the components for which you are responsible for designing.
   • Internal specifications of the components for which you are responsible for implementation
4. [1 copy per group] Implementation Status Report (File name: status_report.pdf)
   • Division of labor: How each group member plans to divide the design of each block that makes up the processor?
   • Current progress toward the final goal and future progress plan

[Check before submission]

• Entirety
  • Does each report have a cover page? Are the title, group number, and name of the member or submitter on the report?
  • Is the structure of chapters and sections organized? Are chapter numbers and chapter titles provided?
  • Are all figures and tables titled and referenced from the text, such as, “...is shown in Figure 1.1.”?
  • Are the repository names and file names as specified?
• Architecture Study Report
  • Does it have a written and graphical explanation of each team's unique design principles?
  • Is there a description of each group's own improvement method and its performance prediction, etc.?
  • Write anything you like in the considerations, etc. section, such as how you came up with the above specification (design principles, methods of improvement), comparisons with other methods, etc.
• System Design Specifications
  • ○ Is the description sufficient so that whoever does the functional design will be able to design something equivalent?
• Functional Design Specifications
  • Is there a description on how you segmented the whole into components?
  • Are the external specifications of each component clear? Are the signal line names, the number of bits in each signal line, and the operation as seen from the outside described?
  • Are the internal specifications of each component clear? Are the signal line names, the number of bits in each signal line, the internal structure, and processing methods described?
• Implementation Status Report
  • Does it describe the division of labor in a clear and reasonable manner?

Final Report

Demonstration [Running demonstration of the processor]

Date and Time: May 31st (Fri) 13:15-16:30

Students will give a presentation (sales talk) on the features of the microcomputer they have built and demonstrate the execution of an application program on the microcomputer.

• The demonstration must be conducted with all group members present.
• Each member of the group must be responsible for a part of the demonstration.

Report [Documentation on the processor you have built]

Submission Deadline: June 7th (Fri) 13:15

Submission Method: Submit the report by creating a release for the tag name (Tag version) called final in the repository of 2024-simple-team[team number] in GitHub Classroom. The assignment is considered submitted when the release is created. To resubmit, you must create a new release with a suffix number such as final-1.

Materials to be Submitted: Report as indicated below and design data of the completed processor. (All project files required for synthesis should be included in the repository.)

Content of the Report: Summarize the following information about the completed processor. Each document should have a cover page. The cover page should indicate the name of the document, the student number and name, and the date of submission, etc. Create a directory named report_final at the top of the repository, and place each report document (PDF format only) in the directory with the file names shown in blue below.

1. [1 copy per group] User's Manual for the Final Deliverables (File name: user_manual.pdf)
   • Refers to an instruction manual, reference manual, or data book.
   • Assuming that the processor is to be made available as an IP core (soft-core processor), the necessary and sufficient information for the use of the processor must be described.
   • Overview, performance and features, instruction set architecture, structure and operation, etc.
   • Make this a complete document by itself (without having to refer to SIMPLE/B).
2. [1 copy per group] Architecture Extension Specifications (File name: extended_spec.pdf)
   • Description of the extended specifications based on the SIMPLE/B basic architecture
     • What extensions have been made?
     • Explain so that extended specifications and functions can be understood from this document alone.
   • Explain the benefit from those extensions.
     • What new thigs will it be able to do? (It is also advisable to explain it with sample codes, etc)
3. [1 copy per group] Performance Evaluation Report (File name: evaluation_report.pdf)
   • Evaluate and report on the final deliverables, the processor, of this exercise with respect to each of the performance metrics. Also report on how each metric has changed (and to what extent it has been improved) with the extended specifications implemented.
     • Circuit area: Number of gates (number of LUTs, total/per component)
     • Clock frequency: (estimate value for actual operation/CAD), critical path
     • Application program performance: Number of program instructions/number of execution instructions/number of execution cycles.
   • Reflect on the results of the evaluation. Discuss the degree of achievement for the design goals set for the architecture study at the time of the mid-term report, the degree of achievement for performance and cost estimation, and guidelines for further improvements.
4. [1 copy per person] Functional Design Specifications (File name: function_status-[student number].pdf)
   • Functional design specifications for the components for which you are responsible for designing (When additional components have been added since the mid-term report)
   • Performance evaluation of the major component for which you are responsible for designing (number of LUTs, delay (CAD estimate), critical path, etc.)
   • Considerations and impressions
     • Discuss the design as a whole, and particularly detailed discussion of the parts for which you are responsible for.
     • Describe the findings and impressions gained through this experiment.
5. [1 copy per group] Implementation Report (File name: implementation_report.pdf)
   • How far the architectural design goals discussed in the mid-term report have been achieved? If any changes were made to the goals and plans, what were the circumstances and intentions behind the changes?
   • Division of labor: How each group member divided the design of each block that makes up the processor?
   • Include the tag name of the repository for 2024-simple-team[team number] in GitHub Classroom for the final design data.

[Check before submission] List of Final Report Checkpoints for TA (txt format, UTF-8)

Also check “Cautionary Points for Design Data Submission.” If any of the ◎ items are not satisfied, you may be instructed to resubmit the design data (especially common are cases where there are no time constraints set or where there are timing violations).

Minimize printing to conserve natural resources and get used to reading online for the sake of the future.

How to Proceed with Hardware Design

Circuit Design Description in Verilog HDL

Introduces typical HDL and explains the basic syntax in Verilog HDL.

Design Flow Using CAD Tools (Project 3HW)

Explains the design flow of Quartus Prime, including how to use it in HDL design and how to execute it on actual machines.
A hands-on Quartus project is published on GitHub as an example of correct data. Refer to it as needed.

Setting and Verifying Timing Constraints

An explanatory handout for time constraints and the usage of TimeQuest Timing Analyzer, a supplementary course offered in AY2019. It may be updated and offered again this year.

AY2019 Second Semester Project 2HW “Logic Design on CAD Tools”

For those who forgot everything during spring vacation...

SIMPLE

SIMPLE Design Resources (ver 4.0: 20200415)

Describes the basic specifications and principles of SIMPLE, which is the architecture of the processor you will design.

Implementation of the SIMPLE Architecture Processor

The instruction set and basic implementation of the SIMPLE architecture are explained using diagrams. In addition, hints are given for the design process.

simple_tools

This is a collection of tools that may be useful for the processor design exercise. Updated as needed?
It is publicly available on GitHub under the MIT License. Issues and pull requests are welcome within the scope of the basic instruction set.

simple_sample

This is a collection of sample programs written in SIMPLE basic instructions. It contains a variety of programs, so use it in accordance with your progress in the project.

simple_assembler

This is a SIMPLE instruction code assembler written in Python.

simple_simulator

This is an instruction level simulator for SIMPLE written in Java. Allows you to verify the functionality of assembly description code. An assembler function is also included in the package.

Tips for Designing

This document can be used as a reference for designing in CAD, so pay attention to it as well.

Frequently Asked Questions and Answers

In short, this is FAQ. If you have any difficulties, take a look. Additional information is added as needed.

HDL Handbook

This is a collection of FAQs and things to pay special attention to in HDL design. Additional information is added as needed.

How to Create RAM for Main Memory

This describes a way to create the main memory for the processor using megafunction. It is essential for SIMPLE design.

Hints for Designing

These are design hints that include somewhat advanced information. You do not have to force yourself to use them if you do not understand them.

Synchronous Design

Tips for synchronous design. (It describes experimental equipment different from the current equipment, and for reference only.

Logic Gates Required to Configure the Processor

Gates you need to know at very minimum and their truth tables. (This should be common knowledge for those who have taken Logical Systems.)

Circuits Required to Configure the Processor

Lists the basic circuits. (This should be common knowledge for those who have taken Logical Systems.)

Mid-term Lecture Materials

Specifies the design problems that were frequently observed when the mid-term report was submitted.

FPGA Board

There are the instruction manuals (in Japanese) for PowerMedusa MU500-RX/RK, an FPGA board from Mitsubishi Electric Micro-Computer Application Software Co., Ltd.
The FPGA on the board is Altera's Cyclone IV family, EP4CE30F23I7N.
(RX210 microcontroller is also equipped, but not used in this project. If you are interested, you can try experimenting with it.)

Each of these materials is listed on PandA.

MU500-RX Set_User's Manual Ver1.1.pdf

Instruction manual for PowerMedusa board MU500-RX/RK (in Japanese)

MU500-RX_Pin-Assignment_Table.xls

Pin assignment table for PowerMedusa board MU500-RX/RK

MU500-7SEG Manual Ver2.pdf

Instruction manual for the 7-SEG LED board attached to PowerMedusa board MU500-RX/RK (in Japanese)

RX_7SEG Pin Assignment for Manual.xls

Pin assignment table for 7-SEG LED board attached to PowerMedusa board MU500-RX/RK

CAD and FPGA

For CAD, Intel PSG (formerly Altera) Quartus Prime 20.1 is used. Note that the information on the Internet is often unreliable due to differences in versions.
The FPGA used is Cyclone IV EP4CE30F23I7N from Altera.

Quartus Prime Download Center

This is the download page for the Lite Edition of Quartus Prime 20.1, which is the tool used in this project. (Standard Edition is installed in the laboratory.)

Online Resources: Intel FPGA Development Tools Support

This is the online document for Intel Quartus Prime. This document is basically about the latest versions of Intel Quartus Prime tools, and be aware that some of the explanations may not make any sense if the version is different. You may find it difficult to navigate through so many resources, but reading the following intensively may be helpful:

• Quartus Prime Standard Edition Handbook
  There are three volumes, each in a separate file, but the useful chapters for the details of this experiment are shown below:
  • Volume 1, Chapter 17: Optimizing the Design Netlist
  • Volume 2, Chapter 1: Constraining Designs
  • Volume 2, Chapter 10: Design Optimization Overview
  • Volume 2, Chapter 12: Timing Closure and Optimization
  • Volume 2, Chapter 13: Power Optimization
  • Volume 2, Chapter 14: Area Optimization
  • Volume 3, Chapter 8: The Intel Quartus Prime Timing Analyzer
  • (Volume 1, Chapter 3: Intel Quartus Prime Incremental Compilation for Hierarchical and Team-Based Design.
  • (Volume 2, Chapter 2: Managing Device I/O pins)
• Timing Analyzer Quick Start Tutorial
• Simulation Quick-Start for ModelSim-Intel FPGA Edition (Intel Quartus Prime Standard Edition)

Cyclone Legacy FPGAs Support

Handbooks and datasheets for the Cyclone device family are available.

Intel Community Forums

This is a so-called Q&A site, and the “FPGA Developers” category is applicable. You might as well ask the whole world in English.

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References

• 富田眞治，中島浩『コンピュータハードウェア』(昭晃堂) ISBN:4785620447
• D.A.Patterson and J.L.Hennessy, "Computer Organization and Design, Fifth Edition" (Morgan Kaufmann) ISBN:9780124077263
• 小林優『入門Verilog HDL記述―ハードウェア記述言語の速習＆実践』(CQ出版) ISBN:4789833984
• 深山正幸『HDLによるVLSI設計―VerilogHDLとVHDLによるCPU設計』(共立出版) ISBN:4320120272

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Link

• Kyoto University
• Faculty of Engineering, Kyoto University
• Undergraduate Course Program of Computer Science, School of Informatics and Mathematical Science
• Intel PSG (Altera)

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Contact: le3hw@kuis.kyoto-u.ac.jp

このコンテンツは，最初に嶋田創先生が作成され，高木一義先生，高瀬英希先生が更新されたものをベースにしています．
ここに感謝の意を表します．